library verilog;
use verilog.vl_types.all;
entity fre_div_021 is
    port(
        D_068           : out    vl_logic;
        CLK_068         : in     vl_logic;
        C_068           : out    vl_logic;
        E_068           : out    vl_logic;
        F_068           : out    vl_logic;
        B_027           : out    vl_logic;
        A_068           : out    vl_logic
    );
end fre_div_021;
